Logic Levels and Thresholds

Digital inputs do not understand abstract 0 and 1 directly. They measure voltage and classify it using guaranteed LOW and HIGH regions. Correct threshold design is what keeps real digital circuits out of random behavior.

Learning Objectives

By the end of this lesson, you should be able to read logic-level datasheet limits, calculate noise margin, explain undefined regions, choose level translation, and recognize when Schmitt-trigger inputs are needed.

The Four Important Limits

Datasheets usually define four voltage limits:

Symbol	Meaning
`VIL(max)`	highest voltage guaranteed to be read as LOW
`VIH(min)`	lowest voltage guaranteed to be read as HIGH
`VOL(max)`	highest output voltage while driving LOW
`VOH(min)`	lowest output voltage while driving HIGH

The undefined zone is between VIL(max) and VIH(min). Do not design signals to sit there.

Example Logic Levels

Typical 5 V TTL-compatible inputs use approximately:

LOW input: 0 V to 0.8 V.
HIGH input: 2.0 V to 5 V.
Undefined: 0.8 V to 2.0 V.

Many CMOS inputs use threshold ratios based on the supply, often around 0.3 VDD for LOW and 0.7 VDD for HIGH, but the datasheet is the authority.

Noise Margin

Noise margin is the voltage error a signal can tolerate while still being read correctly.

$$
NM_H = V_{OH(min)} - V_{IH(min)}
$$

$$
NM_L = V_{IL(max)} - V_{OL(max)}
$$

If a driver has VOH(min) = 4.4 V and the receiver needs VIH(min) = 3.5 V, then:

$$
NM_H = 4.4 - 3.5 = 0.9 V
$$

That is usable headroom for noise, ground shift, and loading effects.

Hysteresis and Slow Edges

A normal input has one threshold region. A Schmitt-trigger input has separate rising and falling thresholds, giving hysteresis.

flowchart LR A[Slow or noisy signal] --> B[Schmitt trigger input] B --> C[Clean digital edge]

Use Schmitt-trigger inputs for buttons, RC timing nodes, long cables, slow sensors, and noisy digital edges. Without hysteresis, a slow signal can chatter near the threshold.

Level Interfacing

When connecting different voltage domains, check both directions.

A 3.3 V output may or may not meet a 5 V input's VIH(min).
A 5 V output can damage a 3.3 V input unless the pin is explicitly 5 V tolerant.
Open-drain buses such as I2C need pull-ups to the correct receiving voltage.
Fast buses often need a proper level translator, not just a resistor divider.

Worked Example: 3.3 V MCU to 5 V Logic

A 3.3 V MCU has VOH(min) = 2.9 V. A 5 V 74HC input needs VIH(min) = 3.5 V.

$$
NM_H = 2.9 - 3.5 = -0.6 V
$$

The negative margin means the connection is not guaranteed. Use a 74HCT input, a buffer, or a level translator.

Common Mistakes

Treating typical thresholds as guaranteed design limits.
Driving 3.3 V pins from 5 V outputs without checking tolerance.
Allowing slow analog ramps into ordinary digital inputs.
Ignoring ground difference between boards.
Leaving inputs floating.

Practical Checks

For every digital interface, record supply voltage, VOH, VOL, VIH, VIL, noise margins, maximum input voltage, pull resistor value, cable length, and whether the edge rate suits the input type.

Summary

Logic thresholds turn analog voltages into digital states. Reliable designs keep signals well inside guaranteed LOW and HIGH regions, preserve noise margin, and use level shifting or hysteresis when the interface needs it.

Mind Map

mindmap root((Logic levels)) Core concept Voltage becomes 0 or 1 Undefined zone is unsafe Datasheet limits rule Applications MCU GPIO Logic ICs Level translation Noisy inputs Formulas NMH equals VOHmin minus VIHmin NML equals VILmax minus VOLmax CMOS thresholds scale with VDD Design rules Stay out of gray zone Check max pin voltage Use Schmitt for slow edges Translate voltage domains Practical checks Measure VOH and VOL Compare VIH and VIL Check grounds Inspect edge speed Common mistakes Using typical values 5 V into 3.3 V pin Floating input No hysteresis